This invention pertains generally to the integration of dielectrics with integrated circuits, and more particularly to reaction barriers between high-k dielectrics and an underlying Group IV semiconductor layer.
Semiconductors are widely used in integrated circuits for electronic devices such as computers and televisions. These integrated circuits typically combine many transistors on a single crystal silicon chip to perform complex functions and store data. Semiconductor and electronics manufacturers, as well as end users, desire integrated circuits that can accomplish more functions in less time in a smaller package while consuming less power.
Most semiconductor memories use an array of tiny capacitors to store data. One approach to expanding the capacity of a memory chip is to shrink the area of each capacitor. However, everything else being equal, a smaller area capacitor stores less charge, thereby making it more difficult to integrate into a useful memory device. One approach to shrinking the capacitor area is to change to a storage dielectric material with a higher permittivity. To the best of our knowledge, past efforts to incorporate high permittivity (high-k) materials into integrated circuits have not proven completely satisfactory.
In another, related area, one concern is the thickness of the gate dielectric used in conventional CMOS circuits. The current drive in a CMOS transistor is directly proportional to the gate capacitance. Since capacitance scales inversely with thickness, higher current drive requires continual reductions in thickness for conventional dielectrics. Present technology uses SiO2 based films with thicknesses near 5 nm. However projections suggest the need for 2 nm films for future small geometry devices. SiO2 gate dielectrics in this thickness regime pose considerable challenges from a manufacturing perspective. Process control of the growth of a 2 nm film requires unprecedented thickness control. At these thicknesses direct tunneling through the SiO2 may occur, although the effect of tunneling current on device performance may not preclude operation. Since the tunnel current depends exponentially on the dielectric thickness, small variations in process control may result in large variations in the tunnel current, possibly leading to localized reliability problems. SiO2 at these thicknesses also provides very little barrier to diffusion. Thus the diffusion of B from doped poly gates, for example, would represent an increasingly difficult problem that might also require a move to new gate dielectrics or gate metals.
The capacitance of a simple parallel plate dielectric with metal electrodes can be expressed as
C=xcex5xcex50A/t
where xcex5 is the dielectric permittivity, xcex50 so is the permittivity of free space, A is the capacitor area and t is the dielectric thickness. In general, the increase in capacitance density (C/A) required for increasing current drive can be accomplished either by decreasing the dielectric thickness t or by increasing the dielectric permittivity xcex5 of the material. Thus, as with storage dielectrics, it is again desirable to change to a material with a higher permittivity.
Although dielectric permittivity is often referred to as the dielectric xe2x80x9cconstantxe2x80x9d k, it is not a constant and may show strong variations with frequency, electric field or temperature. The magnitude of each of the dielectric mechanisms, as well as the speed with which they respond to changes in the applied field will vary. The space charge and dipole components show strong variations at frequencies of a few MHz and below. The ionic component is relatively constant for values well into the GHz region, while at optical frequencies the only remaining component is the electronic polarization. Consideration of these phenomena initially suggests that either ionic or electronic mechanisms may be preferred in high permittivity dielectrics for memory capacitors and gate dielectrics. Although most high permittivity dielectrics have dielectric constants greater than 50, some potentially useful dielectrics have lower permittivity. Thus, for the purposes of this application, high permittivity dielectrics will have dielectric constants greater than or equal to about 20.
This preference for dielectric mechanisms with high frequency response somewhat limits the field of practical high permittivity dielectric materials. This class of materials includes Ta2O5; Nb2O3; Y2O3; TiO2; (Ta2O5)9, (TiO2)1; ZrO2; HfO2; (Hf,Zr)O2; BaTiO3; SrTiO3; and (Ba,Sr)TiO3 or BST. Even though some of these may be considered ferroelectric materials, each of these materials shows promise as a high-k dielectric.
This disclosure will focus on high-k dielectrics. However, many devices will provide suitable performance with elevated dielectric constant (k greater than 7) materials such as Al2O3 and Si3N4, and limited frequency response materials such as lead zirconate titanate (PZT). If performance requirements are satisfied, these dielectrics may be substituted for the high-k dielectrics in the examples below.
The semiconductor industry has tried for several years to integrate high permittivity (high-k) materials into integrated circuits. Although there has been much progress, these prior approaches each have drawbacks or limitations. One recurring problem is preventing unwanted layers from forming between the substrate or first electrode and the high-k dielectric. Unless these layers also have a high permittivity, the overall capacitance is reduced. This can be shown clearly with an illustrative example. For this example, we will use one promising high-k dielectric candidate, Ta2O5 on a silicon layer. Other high-k materials will have different interface details, but will follow the same general analysis.
Ta2O5 has a promising permittivity and reasonable bandgap. However, the lower heat of formation relative to SiO2 immediately suggests that Ta2O5 is not thermodynamically stable next to Si and will decompose to SiO2 at the interface. The capacitance of 2 dielectrics in series (such as a Ta2O5 dielectric layer on an interfacial SiO2 layer) is given by
(1/C)=(1/C1)+(1/C2)
where C1 and C2 are the capacitances of the two layers. From equation 1 we can write (assuming equal area capacitors)
t/xcex5=t1/xcex51+t2xcex52
where t1, t2 represent the thicknesses of the two layers, xcex51,xcex52represent the permittivities of the two layers, and t and xcex5 are the xe2x80x9ceffectivexe2x80x9d thickness and permittivity of the stack. A common parameter used to describe dielectric stacks is the equivalent oxide thickness of the capacitor. This is the theoretical thickness of SiO2 that would be necessary to generate the same capacitance density as the material of interest (ignoring practical issues with thin SiO2 films such as leakage or tunneling effects). Thus,
xe2x80x83teq(SiO2)=xcex5(SiO2)*[t1/xcex51+t2/xcex52]
If the interfacial layer t1 is SiO2, this equation can be rewritten as:
teq(SiO2)=t1+t2*[xcex5(SiO2)/xcex52]
This equation shows that the equivalent (effective) oxide thickness of the stack (and hence the capacitance density) will be limited by the presence of a thin interfacial oxide. Thus, the effective oxide thickness will never be less than the thickness of the interfacial oxide. This minimum effective thickness is independent of the permittivity and thickness of the second layer. This finding is consistent with the extensive body of work performed to try to develop Ta2O5 as a DRAM dielectric. According to Aoyama, in xe2x80x9cLeakage current mechanism of amorphous and polycrystalline Ta2O5 films grown by chemical vapor deposition.xe2x80x9d J. of Electrochemical Society, 1996. 143(3): p. 977-983, the minimum effective oxide thickness achievable with Ta2O5 MIS capacitor structures using Si based electrodes is xcx9c2.5 nm. This is due to the presence of an interfacial oxide formed during the Ta2O5 deposition and/or crystallization anneal steps. Various processes have been attempted to control the nature of the interface between Si and Ta2O5, including strategies for using N2O to nitride the Si surface before Ta2O5 deposition. In all cases to date, however, the capacitance density has been limited by the unwanted presence of an SiO2 layer at the interface. The lower equivalent oxide thickness of 0.7 nm achieved using Ta2O5 with metal electrodes (see Aoyama, T.e.a. xe2x80x9cCharacteristics of thin film Ta2O5 capacitors with Ru bottom electrode.xe2x80x9d in 43rd spring meeting of the Japanese Society of Applied Physics. 1996. Univ. of Tokyo, Japan.) indicates the potential capacitance available if interfacial oxide could be removed. The presence of the interfacial oxide is the dominant difficulty in implementing oxide based dielectrics on Si.
To keep the equivalent thickness low, we have given up the approach of eliminating an interfacial layer. Instead, we form an ultra-thin (such as a monolayer), thermodynamically stable interfacial layer of SiC. This SiC layer acts as a reaction barrier to prevent the formation of a thick SiO2 layer at the interface. This SiC monolayer may add to the overall equivalent oxide thickness. However, this ultra-thin layer will give very little contribution. This deceptively simple approach also has other advantages. SiC""s very stable nature allows its use as a reaction barrier with many high-k dielectrics. SiC deposition is highly conformal and more or less self-terminating, while excess carbon is easily removed. Ultra-thin SiC formation is simple to implement in the manufacturing environment and compatible with existing equipment. When used in conjunction with rugged (textured) polysilicon, the Sixe2x80x94C bonds at the grain boundaries help to prevent the polysilicon grains from coalescing during subsequent processing.
The Sixe2x80x94C reaction has been extensively studied and researchers have used bulk SiC as a semiconductive material. However, this is apparently the first time that anyone has taught the use of an SiC monolayer as a reaction barrier between an oxygen rich dielectric and a silicon layer. This novelty comes in spite of a long-felt need in the semiconductor industry for an effective method to connect silicon to dielectrics (often through an intermediate electrode) that either react with silicon or oxidize silicon. This area has been extensively researched with numerous techniques patented and papers published over the last 10 years. This invention""s novelty can possibly be explained by the fact that most semiconductor production facilities generally regard carbon as a contaminant. They especially avoid forming SiC surface films, due to the difficulty of removing a SiC film from a silicon surface. Additionally, the process for forming bulk SiC is not well suited to forming ultra-thin SiC films.
A method of forming a memory cell in an integrated circuit is disclosed. This method comprises providing a partially completed integrated circuit having a semiconductor layer substantially comprising silicon, where the layer has an exposed face. The method further comprises forming an ultra-thin SiC reaction barrier at the exposed face, and depositing a storage dielectric on the SiC reaction barrier. The method further comprises forming a memory cell comprising the storage dielectric. In some embodiments, this method also comprises removing unreacted carbon by annealing in an oxygen-containing atmosphere after forming the SiC reaction barrier and before depositing the storage dielectric. Typically, the SiC reaction barrier is less than 25 xc3x85 thick, preferably one or two monolayers of SiC. Preferably, the storage dielectric is a high-k material, perhaps containing oxygen. Some suitable storage dielectrics include CeO2; Al2O3; Si3N4; Nb2O3; Y2O3; TiO2; (Ta2O5)9, (TiO2)1; ZrO2; HfO2; BaTiO3; SrTiO3; BST; and PZT. In some embodiments, such as trench capacitors and stack capacitors, the underlying semiconductor layer is not substantially flat.
A method of forming a MIS field-effect transistor (FET) structure in an integrated circuit is also disclosed. This method comprises providing a partially completed integrated circuit having a silicon layer with an exposed face and forming an ultra-thin SiC reaction barrier at the exposed face. The method further comprises depositing a gate dielectric on the SiC reaction barrier, forming a gate electrode on the gate dielectric, and forming a FET comprising the gate dielectric.